Semiconductor device

Details Semiconductor device Semiconductor device

2008-01-15

2008-01-15

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000

Reexamination Certificate

active

07319271

ABSTRACT:
Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and a via formed by filling with a conductive material the inside of a wiring trench formed on the face side of a layer insulation film and a contact hole provided at a bottom portion of the wiring trench. The layer insulation films constituting the plurality of wiring layers are so configured that the layer insulation films are changed in the magnitude of mechanical strength alternately on a wiring layer basis in the lamination direction of the wiring layers.

REFERENCES:
patent: 6313537 (2001-11-01), Lee et al.
patent: 6498384 (2002-12-01), Marathe
patent: 6734561 (2004-05-01), Kawai
patent: 6858936 (2005-02-01), Minamihaba et al.
patent: 11-045887 (1999-02-01), None
Kondo et al., “Low Pressure CMP for reliable porous low-k/Cu integration”, IITC (2003) pp. 86-88.
Nakai et al., “A 65nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 055 μ m2 6T-SRAM Cell and Robust Hybrid-ulk/Cu Interconnects for Mobile Multimedia Applications” IEE. (USA), 2003, pp. 285-288.

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2774460