Low crosstalk substrate for mixed-signal integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...

Reexamination Certificate

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Other Related Categories

C257SE25029, C257S500000, C257S659000, C257SE25031

Type

Reexamination Certificate

Status

active

Patent number

07402884

Description

ABSTRACT:
An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.

REFERENCES:
patent: 5583378 (1996-12-01), Marrs et al.
patent: 5767561 (1998-06-01), Frei et al.
patent: 5889314 (1999-03-01), Hirabayashi
patent: 2001/0023111 (2001-09-01), Yuan
patent: 2003/0059541 (2003-03-01), Ogure
J. Ankarcrona et al. Low resistivity SOI for substrate crosstalk reduction. IEEE Electron Device Lett., vol. 52, pp. 1920-1922 (2005).
P.M. Asbeck et al. GaAlAs/GaAs heterojunction bipolar transistors: issues and prospects for application. IEEE Trans. Electron Devices, vol. 36, pp. 2032-2042 (1989).
K.B. Ashby et al. High Q inductors for wireless applications in a complementary silicon bipolar process. IEEE J. Solid-State Circuits, vol. 31, pp. 4-9 (1996).
K. Benaissa et al. RF CMOS on high-resistivity substrates for system-on-chip applications. IEEE Trans. Electron Devices, vol. 50, pp. 567-576 (2003).
J.N. Burghartz et al. On the design of RF spiral inductors on silicon. IEEE Trans. Electron Devices, vol. 50, pp. 718-729 (2003).
J.N. Burghartz. Progress in RF inductors on silicon—Understanding substrate losses. IEDM Tech. Digest, pp. 523-526 (1998).
T.S. Chen et al. An efficient noise isolation technique for SOC application. IEEE Trans. Electron Devices, vol. 51, pp. 255-260 (2004).
K. Chong et al. High performance inductors integrated on porous silicon. IEEE Electron Device Lett., vol. 26, pp. 93-95 (2005).
E.M. Chow et al. Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates. J. Microelectromech. Syst., vol. 11, pp. 631-640 (2002).
Y. Hiraoka et al. New substrate-crosstalk reduction using SOI substrate. IEEE International SOI Conference, pp. 107-108 (2001).
A. Hürrich et al. COI-CMOS technology with monolithically integrated active and passive RF devices on high resistivitySIMOX substrates. IEEE International SOI Conference, pp. 130-131 (1996).
H. Jiang et al. Reducing silicon-substrate parasitics of on-chip transformers. Proceedings of IEEE Micro Electro Mechanical Systems, Las Vegas, Nevada, pp. 649-652 (2002).
K. Joardar. Signal isolation in biCMOS mixed mode integrated circuits. Bipolar/BiCMOS Circuits and Technology Meeting, pp. 178-181 (1995).
R.A. Johnson et al. Comparison of microwave inductors fabricated on silicon-on-sapphire and bulk silicon. IEEE Microwave and Guided Wave Lett., vol. 6, pp. 323-325 (1996).
M.-D. Ker et al. Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS. IEEE Trans. Electron Devices, vol. 48, pp. 2953-2956 (2001).
M. Kumar et al. Novel isolation structures for TFSOI technology. IEEE Electron Device Lett., vol. 22, pp. 435-437 (2001).
K. Lakdawala et al. Micromachined high-Q Inductors in a 0.18-um copper interconnect low-K dielectric CMOS process. IEEE J. Solid-State Circuits, vol. 37, pp. 394-403 (2002).
S. Lam et al. High-isolation bonding pad design for silicon RFIC up to 20GHz. IEEE Electron Device Lett., vol. 24, pp. 601-603 (2003).
J.P.Z. Lee et al. Substrate cross talk noise characterization and prevention in 0.35 um CMOS technology. IEEE Custom Integrated Circuits Conference, pp. 479-482, (1999).
T. Mizoguchi et al. A 250-pixel SIT image sensor operating in its high-sensitivity mode. IEEE Trans. Electron Devices, vol. 38, pp. 1021-1027 (1991).
O.H. Murphy et al. Design of multiple-metal stacked inductors incorporating an extended physical model. IEEE Trans. Microwave Theory and Techniques, vol. 53, pp. 2063-2072 (2005).
M. Park et al. The detailed analysis of high Q CMOS-compatible microwave spiral inductors in silicon technology. IEEE Trans. Electron Devices, vol. 45, pp. 1953-1959 (1998).
M. Pfost et al. An experimental study on substrate coupling in bipolar/biCMOS technologies. IEEE J. Solid-State Circuits, vol. 39, pp. 1755-1763 (2004).
N.P. Pham et al. IC-compatible two-level bulk micromachining process module for RF silicon technology. IEEE Trans. Electron Devices, vol. 48, pp. 1756-1764 (2001).
J.P. Raskin et al. Substrate crosstalk reduction using SOI technology. IEEE Trans. Electron Devices, vol. 44, vol. 44, pp. 2252-2261 (1997).
R.P. Ribas et al. Micromachined microwave planar spiral inductors and transformers. IEEE Trans. Microwave Theory and Techniques, vol. 48, pp. 1326-1335 (2000).
S.M. Sinaga et al. Through-substrate trenches for RF isolation in wafer-level chip-scale package. Electronics Packaging Technology Conference, pp. 13-17 (2004).
R. Singh. A review of substrate coupling issues and modeling strategies. IEEE Custom Integrated Curcuits Conference, pp. 491-498 (1998).
S. Stefanou et al. Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology. IEEE Trans. Electron Devices, vol. 51, pp. 486-491 (2004).
D.D. Tang et al. The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips. IEDM Tech. Digest, pp. 673-676 (2003).
N.J. Thomas et al. High performance thin-film silicon-on-insulator CMOS transistors in porous anodized silicon. IEEE Electron Device Lett., vol. 10, pp. 129-131 (1989).
K.H. To et al. Comprehensive study of substrate noise isolation for mixed-signal circuits. IEDM Tech. Digest, pp. 519-522 (2001).
J.H. Wu et al. A through-wafer interconnect in silicon for RFICs. IEEE Trans. Electron Devices, vol. 51, pp. 1765-1771 (2004).
S.M. Yim et al. The effects of a ground shield on the characteristics and performance of spiral inductors. IEEE J. Solid-State Circuits, vol. 37, pp. 237-244 (2000).
C.P. Yue et al. On-chip spiral inductors with patterned ground shields for Si-based RF IC's. IEEE J. Solid-State Circuits, vol. 33, pp. 743-752 (1998).

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