Electric heating – Heating devices – With power supply and voltage or current regulation or...
Reexamination Certificate
2011-03-08
2011-03-08
Hoang, Tu B (Department: 3742)
Electric heating
Heating devices
With power supply and voltage or current regulation or...
C219S444100, C219S448110, C219S448120, C700S300000
Reexamination Certificate
active
07902485
ABSTRACT:
Temperature setting of a thermal plate is performed so that the line width of a resist pattern is uniformly formed within a wafer. The thermal plate of a PEB unit is divided into a plurality of thermal plate regions so that the temperature can be set for each of the thermal plate regions. A temperature correction value for adjusting the temperature within the wafer mounted on the thermal plate is set for each of the thermal plate regions of the thermal plate. The temperature correction value for each of the thermal plate regions of the thermal plate is set after calculation by a calculation model created from a correlation between a line width of the resist pattern formed by thermal processing on the thermal plate and the temperature correction value. The calculation model M calculates the temperature correction value to make the line width uniform within the wafer, based on a line width measured value of the resist pattern.
REFERENCES:
patent: 6072162 (2000-06-01), Ito et al.
patent: 2003/0054642 (2003-03-01), Kagotani et al.
patent: 1 308 783 (2003-05-01), None
patent: 2000 82661 (2000-03-01), None
patent: 2000 349018 (2000-12-01), None
patent: 2001 168022 (2001-06-01), None
patent: 2002 184682 (2002-06-01), None
patent: 2003 209050 (2003-07-01), None
patent: 2004 235469 (2004-08-01), None
Machine Translation of JP2003-209050.
U.S. Appl. No. 12/103,276, filed Apr. 15, 2008, Jyousaka, et al.
Search and Examination Report Dec. 19, 2008, in Singapore Patent Application No. 200705802-7 filed Feb. 8, 2006 , which encloses a Search and Examination report issued Nov. 21, 2008, in Austrian Patent Application No. 200705802-7 filed Feb. 8, 2006.
Aili Ting, “Temperature rise of the silicon mask-PMMA resist assembly during LIGA exposure,” Proceedings of the SPIE - The International Society for Optical Engineering, vol. 5715, pp. 47-58 (2005); INSPEC/IEE - 9354929;ABSTRACT.
M. D. Smith et al., “Modeling the impact of thermal history during post exposure bake on the lithographic performance of chemically amplified resists,” Proceedings of the SPIE - The International Society for Optical Engineering, vol. 4345, pp. 1013-1021 (2005); INSPEC/IEE - 7227891;ABSTRACT.
Jyousaka Megumi
Tadokoro Masahide
Tomita Hiroshi
Hoang Tu B
Jennison Brian
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Tokyo Electron Limited
LandOfFree
Temperature setting method of thermal processing plate,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Temperature setting method of thermal processing plate,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Temperature setting method of thermal processing plate,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2769258