Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2008-01-01
2008-01-01
Jones, Hugh (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C703S016000, C703S017000
Reexamination Certificate
active
07315806
ABSTRACT:
A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there are negative constraints in logic elements. In one example embodiment, the technique adjusts negative timing constraints by grouping the timing constraints based on associated output terminals in a digital logic circuit. The NCC is then applied to each grouped constraint to correct for path delays and resulting timing inaccuracy during an event driven simulation.
REFERENCES:
IEEE Standard for VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification; 1995; pp. 10, 19, 34-36, 53-56.
Babu Javaji Sunil
Muthalif Abdul MJ
Rao Raghavendra N
Brady W. James
Jones Hugh
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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