Low level clamp circuit

Details Low level clamp circuit Low level clamp circuit

1989-07-20

1990-10-30

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307268, 307555, 307565, H03K 508, H03K 400

Patent

active

049670999

ABSTRACT:
In order to stabilize an intermediate level of a clock having at three pulse output levels by a low level clamp circuit, a first negative bias driving circuit outputs a pulse with an amplitude corresponding to a first supply voltage (E.sub.cc). The outputted pulse is clamped by a first diode and then rectified/smoothed by a second diode and a capacitor to obtain a clamp level determining a negative bias dc output (Edc). A second intermediate level driving circuit (2) outputs a pulse with an amplitude corresponding to a voltage lower than the first supply voltage to obtain an intermediate level clock pulse to be stabilized. The low level of the intermediate level clock is further clamped to the obtained negative bias dc output by a third diode. The intermediate level is stabilized against supply voltage and/or temperature fluctuations, without use of any Zener diode.

REFERENCES:
patent: 3805095 (1974-04-01), Lee et al.
patent: 3811053 (1974-05-01), Habib
patent: 3970777 (1976-07-01), Bradford et al.
patent: 4167682 (1979-09-01), O'Dea
patent: 4369466 (1983-01-01), Matsuzaki et al.
patent: 4451747 (1984-05-01), Rucker

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