Method and apparatus for removing timing hazards in a circuit de

Details Method and apparatus for removing timing hazards in a circuit de Method and apparatus for removing timing hazards in a circuit de

1996-05-31

1998-09-01

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364578, 395500, 395568, 371 221, G06F 1750

Patent

active

058019553

ABSTRACT:
A computer system is programmed with logic for automatically removing timing hazards from a circuit design. More specifically, the computer system is programmed with logic for automatically detecting and resolving clock gating as well as clock division timing hazards from the circuit design. In one embodiment, the computer system is further programmed with logic for logically organize timing hazards into levels, after the clock gating timing hazards have been resolved, and then resolving clock division timing hazards recursively. In one adaptation, the computer system is a component of a hardware emulation system.

REFERENCES:
patent: 5377334 (1994-12-01), Boldt et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5493505 (1996-02-01), Banerjee et al.
patent: 5517506 (1996-05-01), Underwood et al.
patent: 5583787 (1996-12-01), Underwood et al.
Subrahmanyam et al., "Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL Environment", IEEE, 1993, pp. 235-241.

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