Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2008-01-01
2008-01-01
Pert, Evan (Department: 2826)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S107000, C438S329000, C438S584000, C438S800000, C257S700000, C257S758000, C361S763000
Reexamination Certificate
active
07314780
ABSTRACT:
A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.
REFERENCES:
patent: 5796587 (1998-08-01), Lauffer et al.
patent: 6392898 (2002-05-01), Asai et al.
patent: 6480370 (2002-11-01), Koning et al.
patent: 6487088 (2002-11-01), Asai et al.
patent: 6545353 (2003-04-01), Mashino
patent: 6611419 (2003-08-01), Chakravorty
patent: 6764931 (2004-07-01), Iijima et al.
patent: 6828224 (2004-12-01), Iijima et al.
patent: 6939738 (2005-09-01), Nakatani et al.
patent: 6952049 (2005-10-01), Ogawa et al.
patent: 7239014 (2007-07-01), Ogawa et al.
patent: 11-260148 (1999-09-01), None
patent: 2000-208945 (2000-07-01), None
patent: 2001-223301 (2001-08-01), None
patent: 2001-267751 (2001-09-01), None
Japanese Office Action for corresponding Japanese Patent Application No. JP2003-058792 dated May 31, 2007.
Iijima Takahiro
Rokugawa Akio
Shimizu Noriyoshi
Erdem Fazli
Pert Evan
Shinko Electric Industries Co. Ltd.
Stass & Halsey LLP
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