Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

2000-03-08

2000-12-19

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365220, G11C 800

Patent

active

061635014

ABSTRACT:
A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentially transferred to the same peripheral data line as the one of the peripheral data lines, to which the head data have been transferred. Thus, it is possible to decrease the number of peripheral data lines to reduce the chip size of an SDRAM while adopting a pre-fetch system for accelerating a data transfer cycle.

REFERENCES:
patent: 5469558 (1995-11-01), Lieberman et al.
patent: 5784705 (1998-07-01), Leung
patent: 5835443 (1998-11-01), Fujita
patent: 5901109 (1999-05-01), Miura
patent: 6011748 (2000-01-01), Lepejian et al.
H. Yoo, "A Study of Pipeline Architectures for High-Speed Synchronous Dram's", IEEE Journal of Solid State Circuits, vol. 32, No. 10, pp. 1597-1603, (1997).

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