Semiconductor memory device having a common column decoder share

Details Semiconductor memory device having a common column decoder share Semiconductor memory device having a common column decoder share

1999-10-14

2000-12-19

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 800

Patent

active

061634964

ABSTRACT:
A column switching circuit that connects a bit line pair and sub-data buses is constituted of first through fourth N transistors. The first and third N transistors are connected in series to a first bit line of the bit line pair whereas the second and fourth N transistors are connected in series to the second bit line of the bit line pair. The gate of the first N transistor and the gate of the second N transistor are connected to commonly receive a column switch selection signal. The gate of the third N transistor and the gate of the fourth N transistor are commonly connected to a column line. By adopting this structure, the generation of a through current is prevented from occurring between the bit line pair and the sub-data buses to result in a reduction in power consumption and miniaturization of the chip is achieved.

REFERENCES:
patent: 5687132 (1997-11-01), Rao
patent: 5953257 (1999-09-01), Inoue et al.
patent: 6016280 (2000-01-01), Maesako et al.

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