Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-04-22

2008-04-22

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Powering

C365S229000, C365S227000, C365S189090, C365S185240

Reexamination Certificate

active

07362646

ABSTRACT:
A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

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Masanao Yamaoka, et al., “A 300MHz 25μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor”, 2004 IEEE International Solid-State Circuits Conference, Session 27, 27.2, Feb. 18, 2004, 10 pages.
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