Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2011-08-30
2011-08-30
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185240, C365S185220
Reexamination Certificate
active
08009470
ABSTRACT:
A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
REFERENCES:
patent: 7046568 (2006-05-01), Cernea
patent: 7310255 (2007-12-01), Chan et al.
patent: 7447081 (2008-11-01), Chan et al.
patent: 7843725 (2010-11-01), Sarin et al.
patent: 2004/0109357 (2004-06-01), Cernea et al.
Iwai Makoto
Nakamura Hiroshi
Kabushiki Kaisha Toshiba
Lam David
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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