Method of alignment for semiconductor memory device

Details Method of alignment for semiconductor memory device Method of alignment for semiconductor memory device

1988-11-28

1992-03-03

James, Andrew J.

357 239, 357 51, H01L 2968

Patent

active

050937022

ABSTRACT:
A semiconductor memory cell with an N-type conductivity capacitance implant region self-aligned with a polysilicon transfer gate is disclosed. In a first embodiment after a blanket capacitance implant, formation of the capacitance storage polysilicon gate and an overlying insulating layer, a plasma etch is used to define specific regions of the capacitance implant. In a second embodiment, a complementary implant step is used after formation of the insulating layer over the capacitance storage polysilicon gate. Subsequently, in both embodiments, a transfer gate is formed with an edge surface adjacent to and abutting the insulating layer over the capacitance storage gate and substantially aligned with an edge surface of the capacitance implant region.

REFERENCES:
patent: 4451841 (1984-05-01), Hori et al.
patent: 4763178 (1988-08-01), Sakui et al.

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