Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-15
2011-03-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S107000, C716S111000, C716S112000, C716S124000, C716S136000
Reexamination Certificate
active
07908576
ABSTRACT:
A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes:a) Providing a reprogrammable logic device (RPLD) with an RPLD-interface and programmable external interfaces PXIFs respectively connected to the PITs.b) Providing a simulation software tool.c) Disabling all PXIFs via RPLD-interface. (For each disabled PXIF, identifying HDEs connected to the PXIF and appending their test benches with stimuli and responses to form appended test benches.d) Progressively verifying and validating all HSEs against the functional validation specification following an upward movement along the SHLs.
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Chang Chioumin M.
Huang Thomas B.
Haynes and Boone LLP
INPA Systems, Inc.
Kwok Edward C.
Siek Vuthe
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