Plasma display panel driving method and plasma display device

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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C345S067000, C345S068000

Reexamination Certificate

active

07365710

ABSTRACT:
A PDP driving method. A falling ramp voltage is applied to a scan electrode so as to reset a state of wall charges of a discharge cell during a reset period. In this instance, a sustain electrode is maintained at a high voltage during an initial period for applying the falling ramp voltage, and the voltage at the sustain electrode is reduced to a normal voltage at a latter part of the period for applying the falling ramp voltage. Accordingly, the voltage applied to an address electrode is reduced in an address period since an erased amount of the wall charges of the address electrode is reduced during the reset period.

REFERENCES:
patent: 5745086 (1998-04-01), Weber
patent: 7012579 (2006-03-01), Choi
patent: 2000-305510 (2000-11-01), None
patent: 2003-295814 (2003-10-01), None
Patent Abstracts of Japan for Publication No. 2000-305510, Date of publication of application Nov. 2, 2000,, in the name of K. Ito et al.
Patent Abstracts of Japan for Publication No. 2003-295814; Date of publication of application Oct. 15, 2003, in the name of Mitsuyoshi Makino.

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