Voltage-stable sub-.mu.m MOS transistor for VLSI circuits

Details Voltage-stable sub-.mu.m MOS transistor for VLSI circuits Voltage-stable sub-.mu.m MOS transistor for VLSI circuits

1989-01-03

1990-10-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 30, 437 41, 148DIG126, H01L 21266

Patent

active

049668595

ABSTRACT:
A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.

REFERENCES:
Yoshida et al., "Thermal Stability and Secondary Breakdown in Planar Power MOSFET's," IEEE Trans. on Electron Devices, vol. ED-27, No. 2, 2/80, pp. 395-398.
Konaka et al., "Suppression of Anomalous Drain Current in Short Channel MOSFET," Jap. Jour. Applied Physics, vol. 18 (1979), Supplement 18-1, pp. 27-33.
IEEE Journal of Sol. Stat. Circuits vol. Sc-9 No. 5, Oct., 1974, pp. 256-268.
IEEE Trans. on Elecktro Devices vol. ED-24, No. 3, Mar., 1977, pp. 196-204.

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