Reprogrammable instruction set accelerator

Details Reprogrammable instruction set accelerator Reprogrammable instruction set accelerator

1995-04-05

1998-04-07

Swann, Tod R.

395376, G06F 1576, G06F 930

Patent

active

057376310

ABSTRACT:
A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources. A condition code register is coupled to instruction fetching resources, and connected to receive condition codes from both the defined execution unit and from the programmable execution unit. The programmable execution unit includes logic to signal the instruction fetching resources to provide a next instruction when execution of the programmed instruction is done. Resources for accessing the configuration store to program the programmable execution unit are provided, which can utilize the internal buses of the data processor or be completely independent of them.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 5109503 (1992-04-01), Cruickshank et al.
patent: 5301344 (1994-04-01), Kolchinsky
patent: 5321845 (1994-06-01), Sawase et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5386518 (1995-01-01), Reagle et al.
patent: 5430734 (1995-07-01), Gilson
patent: 5471593 (1995-11-01), Branigin
patent: 5511173 (1996-04-01), Yamaura et al.
patent: 5517628 (1996-05-01), Morrison et al.
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5574930 (1996-11-01), Halverson, Jr. et al.
DeHon, A. "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century", M.I.T. Transit Project, Transit Note #100, from internet site http://www.ai.mit.edu/projects/transit/tn100/tn100.html, Jan. 29, 1994.
French, P. et al. "A Self-Reconfiguring Processor", Proceedings from 1993 Workshop on FPGAs for Custom Computing Machines, IEEE, pp. 50-59, 1993.
Iseli, C. et al. "Spyder: A Reconfigurable VLIW Processor using FPGAs", Proceedings from 1993 Workshop on FPGAs for Custom Computing Machines, IEEE, pp. 17-24, 1993.
Casselman, S. "Virtual Computing and The Virtual Computer", Proceedings from 1993 Workshop on FPGAsfro Custom Computing Machines, pp. 43-48, 1993.
Trimberger, S. "A Reprogrammable Gate Array and Applications", Proceedings of the IEEE, pp. 1030-1041, Jul. 1993.
Hennessy J. et al. Computer Architecture: A Quantitative Approach, Chapter 5, Appendix E, 1990.
Box, B., "Field Programmable Gate Array Based Reconfigurable Preprocessor", Apr. 10, 1994; IEEE, pp. 40-48.
DeHon, A., "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century", Apr. 10, 1994, IEEE, pp. 31-39.
Thorson, M., "General-Purpose Coprocessors", E-Mail Transcript, Jul. 3, 1992, 5 pages.
Razdan, R., "PRISC: Programmable Reduced Instruction Set Computers", Doctor of Philosophy Thesis, May 1994, 116 pages.
Razdan, R.; Brace, K; and Smith, M.; "PRISC Software Acceleration Techniques", IEEE, May 1994, pp. 145-149.
Trimberger, S., "Field-Programmable Gate Array Technology", Design Applications, Section 2.6, pp. 68-90, Copyright 1994.
Wirthlin, M., Hutchings, Brad, Gilson, K., "The Nano Processor: a Low Resource Reconfigurable Processor", Apr. 10, 1994, IEEE, pp. 23-30.

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