Low stress barrier layer removal

Details Low stress barrier layer removal Low stress barrier layer removal

Filed on

2008-05-13

Date issued

2008-05-13

Examiner

Smith, Bradley K (Department: 2891)

Patent Class

Semiconductor device manufacturing: process

SubClass

Chemical etching

SubSubClass

Combined with the removal of material by nonchemical means

Other Related Categories

C257SE21239

Type

Reexamination Certificate

Status

active

Patent number

07371685

Description

ABSTRACT:
Apparatus and methods of fabricating an interconnect in a dielectric material, such as by a damascene or dual damascene processes. In specific, with the use of a barrier layer, such as to contain copper-containing materials used in the fabrication of the interconnect, a slurry jet is used to remove the barrier layer without significantly damaging underlying dielectric material. Such a process is particularly useful when low-k dielectrics are used as the dielectric material, as low-k dielectrics can be easily damaged by known barrier layer removal techniques.

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Ying Li & S. V. Babu, “Copper and Tantalum Chemical-Mechanical Planarisation: Some Recent Progress,” Semiconductor Fabtech, 13th Edition, Mar. 2001, pp. 259-261.

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