Method of improving a shallow trench isolation gapfill process

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S296000, C438S424000, C438S701000, C257SE21540, C257SE21546, C257SE21574

Reexamination Certificate

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07989309

ABSTRACT:
A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth.

REFERENCES:
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patent: 6833602 (2004-12-01), Mehta
patent: 2001/0026980 (2001-10-01), Mizuo
patent: 2003/0153136 (2003-08-01), Matsumoto et al.
patent: 2004/0157384 (2004-08-01), Blanchard
patent: 2005/0196947 (2005-09-01), Seo et al.
patent: 2007/0111546 (2007-05-01), Iyer et al.
patent: 1531057 (2004-09-01), None
Office Action of Chinese Application No. 200610026323.3., dated Apr. 4, 2008, 10 pages total (English translation not included).

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