Semiconductor memory device and manufacturing method of the...

Details Semiconductor memory device and manufacturing method of the... Semiconductor memory device and manufacturing method of the...

2011-06-28

2011-06-28

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S185130

Reexamination Certificate

active

07969760

ABSTRACT:
The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

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