Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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Details

C257S067000, C257S686000, C257SE27064, C257S506000

Reexamination Certificate

active

07982250

ABSTRACT:
A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.

REFERENCES:
patent: 4472729 (1984-09-01), Shibata et al.
patent: 4933298 (1990-06-01), Hasegawa
patent: 5028976 (1991-07-01), Ozaki et al.
patent: 5422302 (1995-06-01), Yonehara et al.
patent: 5643801 (1997-07-01), Ishihara et al.
patent: 5877034 (1999-03-01), Ramm et al.
patent: 5976953 (1999-11-01), Zavracky et al.
patent: 6037635 (2000-03-01), Yamazaki
patent: 6372609 (2002-04-01), Aga et al.
patent: 6380046 (2002-04-01), Yamazaki
patent: 6424020 (2002-07-01), Vu et al.
patent: 6717180 (2004-04-01), Yamazaki et al.
patent: 6821826 (2004-11-01), Chan et al.
patent: 6908797 (2005-06-01), Takano
patent: 7105394 (2006-09-01), Hachimine et al.
patent: 7199024 (2007-04-01), Yamazaki
patent: 7312487 (2007-12-01), Alam et al.
patent: 2004/0217433 (2004-11-01), Yeo et al.
patent: 2005/0260800 (2005-11-01), Takano
patent: 11-163363 (1999-06-01), None
patent: 2000-124092 (2000-04-01), None
patent: 2003-273240 (2003-09-01), None
Jung et al., “Highly Cost Effective and High Performance 65nm S3(Stacked Single-crystal Si) SRAM Technology with 25F2, 0.16um2Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications,” 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 220-221.
Hayashi, et al., “A New Three Dimensional IC Fabrication Technology, Stacking Thin Film Dual-CMOS Layers,” IEDM 1991, pp. 657-660.

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