Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2011-01-04
2011-01-04
Luu, Chuong A. (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S347000, C257S292000
Reexamination Certificate
active
07863616
ABSTRACT:
A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate line and a gate line wiring area. A passivation layer is formed on the entire substrate and patterned to form two contact holes in the passivation layer on the silicon layer at the gate area, and partions of the passivation layer at the gate line and at the gate line wiring areas are removed. An ion implanting layer and a metal layer are formed on the substrate and patterned to form a source region, a drain region, a data line, a data line wiring area and a second layer of the gate line wiring area. A pixel electrode is formed on the passivation layer and electrically coupled to the drain region. Therefore, the TFT array can be fabricated by only four masks.
REFERENCES:
patent: 7323714 (2008-01-01), Kato et al.
patent: 2002/0019082 (2002-02-01), Wong
patent: 01133182 (2003-03-01), None
patent: 1405865 (2003-03-01), None
patent: 1355561 (2006-06-01), None
Industrial Technology Research Institute
Jianq Chyun IP Office
Luu Chuong A.
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