Information processor and instruction fetch control method

Details Information processor and instruction fetch control method Information processor and instruction fetch control method

2011-01-25

2011-01-25

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction fetching

Reexamination Certificate

active

07877577

ABSTRACT:
In implementing an encryption algorithm or the like in a computer, it is difficult to align timing at which an instruction is executed regardless of presence or absence of branch in a case of including a conditional branch instruction. In order to solve the problem, provided is an information processor (1), including: an instruction fetch unit (instruction fetch circuit200) that fetches an instruction code to be executed to output the fetched instruction code; and an instruction decode unit (instruction decode circuit300) that decodes the instruction code that is output from the instruction fetch unit, in which the instruction decode unit outputs, upon detection of the instruction code being a conditional branch instruction, a control signal to the instruction fetch unit so that fetch timing of the successive instruction code becomes identical with each other regardless of the presence or absence of the branch due to the branch condition.

REFERENCES:
patent: 6275929 (2001-08-01), Blum et al.
patent: 6564316 (2003-05-01), Perets et al.
patent: 6625737 (2003-09-01), Kissell
patent: 7447916 (2008-11-01), Liardet
patent: 2002/0029346 (2002-03-01), Pezeshki et al.
patent: 2002/0124178 (2002-09-01), Kocher et al.
patent: 2003/0115478 (2003-06-01), Feyt
patent: 2004/0064715 (2004-04-01), Kaminaga et al.
patent: 2004/0162993 (2004-08-01), Teglia
patent: 2004/0172518 (2004-09-01), Saruwatari et al.
patent: 2005/0108507 (2005-05-01), Chheda et al.
patent: 2005/0198480 (2005-09-01), Ukai et al.
patent: 2003-502905 (2003-01-01), None
patent: 2006-11723 (2006-01-01), None
Itoh, K etal., A Practical Countermeasure against Address-bit Differential Analysis,2003, Springer-Verlag,pp. 382-396.
Superieure, E.N. etal., Reisistance against Differential Power Analysis for Elliptic Curve Cryptosystems, 1999, Springer-Verlag, pp. 292-302.
Paul Kocher, Joshua Jaffe, and Benjamin Jun, “Differential Power Analysis”, Lecture Notes in Computer Science; vol. 1666, Proceedings of the 19th Annual International Cryptology Conferences on Advances in Cryptology, Year of Publication: 1999; Cryptography Research, Inc.

Affiliated with

Also associated with

Rating

Information processor and instruction fetch control method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Information processor and instruction fetch control method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processor and instruction fetch control method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2733795