Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-08-16
2011-08-16
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S112000, C716S116000, C716S126000, C716S128000, C716S130000, C716S137000, C716S138000, C714S725000
Reexamination Certificate
active
08001511
ABSTRACT:
A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
REFERENCES:
patent: 5787007 (1998-07-01), Bauer
patent: 6157213 (2000-12-01), Voogel
patent: 6160418 (2000-12-01), Burnham
patent: 6204689 (2001-03-01), Percey et al.
patent: 6215327 (2001-04-01), Lyke
patent: 6216257 (2001-04-01), Agrawal et al.
patent: 6218864 (2001-04-01), Young et al.
patent: 6359466 (2002-03-01), Sharpe-Geisler
patent: 6396303 (2002-05-01), Young
patent: 6448808 (2002-09-01), Young et al.
patent: 6944809 (2005-09-01), Lai et al.
patent: 7002828 (2006-02-01), Santin et al.
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 7088134 (2006-08-01), Agrawal et al.
patent: 7095253 (2006-08-01), Young
patent: 7107565 (2006-09-01), Lindholm et al.
patent: 7132851 (2006-11-01), Young
patent: 7181718 (2007-02-01), Bilski et al.
patent: 7187200 (2007-03-01), Young
patent: 7190190 (2007-03-01), Camarota et al.
patent: 7193433 (2007-03-01), Young
patent: 7196543 (2007-03-01), Young et al.
patent: 7199610 (2007-04-01), Young et al.
patent: 7202697 (2007-04-01), Kondapalli et al.
patent: 7202698 (2007-04-01), Bauer et al.
patent: 7205790 (2007-04-01), Young
patent: 7215138 (2007-05-01), Kondapalli et al.
patent: 7218139 (2007-05-01), Young et al.
patent: 7218140 (2007-05-01), Young
patent: 7218143 (2007-05-01), Young
patent: 7221186 (2007-05-01), Young
patent: 7233168 (2007-06-01), Simkins
patent: 7251804 (2007-07-01), Trimberger
patent: 7253658 (2007-08-01), Young
patent: 7256612 (2007-08-01), Young et al.
patent: 7265576 (2007-09-01), Kondapalli et al.
patent: 7268587 (2007-09-01), Pham et al.
patent: 7274214 (2007-09-01), Young
patent: 7276934 (2007-10-01), Young
patent: 7279929 (2007-10-01), Young
patent: 7284226 (2007-10-01), Kondapalli
patent: 7301824 (2007-11-01), New
patent: 7310758 (2007-12-01), Cossoul et al.
patent: 7314174 (2008-01-01), Vadi et al.
patent: 7337422 (2008-02-01), Becker et al.
patent: 7339400 (2008-03-01), Walstrum et al.
patent: 7345507 (2008-03-01), Young et al.
patent: 7402443 (2008-07-01), Pang et al.
patent: 7412635 (2008-08-01), Trimberger
patent: 7424655 (2008-09-01), Trimberger
patent: 7491576 (2009-02-01), Young et al.
patent: 7498192 (2009-03-01), Goetting et al.
patent: 7620863 (2009-11-01), Trimberger
patent: 7849435 (2010-12-01), Trimberger
patent: 2003/0116835 (2003-06-01), Miyamoto et al.
patent: 2004/0060032 (2004-03-01), McCubbrey
patent: 2005/0112614 (2005-05-01), Cook et al.
patent: 2007/0035330 (2007-02-01), Young
patent: 2007/0204252 (2007-08-01), Furmish et al.
Xilinx, Inc.; U.S. Appl. No. 11/334,341 by Goetting et al.; filed Jan. 17, 2006.
Xilinx, Inc.; U.S. Appl. No. 11/333,990 by Young et al.; filed Jan. 17, 2006.
Bauer Trevor J.
Goetting F. Erich
Lindholm Jeffrey V.
Talley Bruce E.
Tanikella Ramakrishna K.
Cartier Lois D.
Maunu LeRoy D.
Rossoshek Helen
Xilinx , Inc.
LandOfFree
Methods of implementing and modeling interconnect lines at... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of implementing and modeling interconnect lines at..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of implementing and modeling interconnect lines at... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2729963