Bumpless flip-chip assembly with a complaint interposer...

Details Bumpless flip-chip assembly with a complaint interposer... Bumpless flip-chip assembly with a complaint interposer...

2011-03-22

2011-03-22

Ho, Tu-Tu V (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S690000, C257S698000, C257SE23027, C438S610000, C438S119000

Reexamination Certificate

active

07911057

ABSTRACT:
Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate. The compressive force may be obtained from forces generated by thermal expansion properties of the molding compound and package substrate, metal clips or combinations, thereof.

REFERENCES:
patent: 4820376 (1989-04-01), Lambert et al.
patent: 5345365 (1994-09-01), Herndon et al.
patent: 2002/0105092 (2002-08-01), Coyle
patent: 2003/0102154 (2003-06-01), Haba
patent: 2003/0186572 (2003-10-01), Hougham et al.
patent: 804171 (1958-11-01), None
JEDEC Design Standard “Design Requirements for Outlines of Solid State and Related Products” JEDEC Publication No. 95, Design Guide 4.2, pp. 1-22.

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