Reconfigurable dual texture pipeline with shared texture cache

Details Reconfigurable dual texture pipeline with shared texture cache Reconfigurable dual texture pipeline with shared texture cache

2011-08-16

2011-08-16

Caschera, Antonio (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics processing

Attributes

C345S506000, C345S519000, C345S552000, C345S557000, C345S606000, C345S608000, C345S609000, C382S260000

Reexamination Certificate

active

07999821

ABSTRACT:
Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

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