Parity and syndrome generation for error detection and correctio

Details Parity and syndrome generation for error detection and correctio Parity and syndrome generation for error detection and correctio

1984-03-05

1985-11-26

Fleming, Michael R.

Excavating

371 38, G06F 1100

Patent

active

045557845

ABSTRACT:
A parity and/or syndrome generator generates a block parity check for the detection and/or correction of errors in a multi-channel digital data communication system using a linear code or a coset of such code in which data and parity bytes are intended to be digitally encoded in n by m bit data blocks to form a respective codeword in n parallel bytes of m bits in serial order of significance in the form of a codeword having n elements represented by respective bytes in the Galois field GF(2.sup.m), such Galois field being defined by an m-order field generator polynomial in integral powers of z between z.sup.0 and z.sup.m, where z is the inverse of the delay operator z.sup.-1 of such Galois field. A first circuit produces a first partial parity check for the bit of such significance in each of the n elements of the respective codeword. A second circuit sums in the Galois field over all elements of the codeword the first partial parity checks to form a second partial parity check. A third circuit multiplies the bit content of each of a plurality of m-bit registers by the inverse of the delay operator in the Galois field and produces respective m-bit products and sums the products with the second partial parity checks to form a third parity check. Clock pulses synchronously clock the data block bits in the order of significance byte-parallel into the first circuit, clock the third parity check into the m-bit registers, and clear the m-bit registers after m bits.

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