Semiconductor memory device

Static information storage and retrieval – Addressing

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365 72, G11C 800

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045557780

ABSTRACT:
Disclosed is a semiconductor memory device in which a group of memory cells consists of a plurality of memory sections, each memory section is provided with a first data line, and a second data line is provided for connecting together the first data lines.

REFERENCES:
patent: 4368523 (1983-01-01), Kawate
Yoshimoto, et al., "A 64Kb Full CMOS RAM with Divided Word Line Structure", IEEE International Solid-State Circuits Conference, ISSCC, pp. 58-59, Feb. 23, 1983.
Watanabe, et al., "A Battery Backup 64K CMOS RAM with Double Level Aluminum Technology" IEEE International Solid-State Circuits Conference, ISSCC, pp. 60-61, Feb. 23, 1983.

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