Semiconductor memory device realizing a channel voltage...

Details Semiconductor memory device realizing a channel voltage... Semiconductor memory device realizing a channel voltage...

2011-01-11

2011-01-11

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185280, C365S185020, C365S185030, C365S185120, C365S185110

Reexamination Certificate

active

07869280

ABSTRACT:
A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

REFERENCES:
patent: 6859395 (2005-02-01), Matsunaga et al.
patent: 7079437 (2006-07-01), Hazama et al.
patent: 7630251 (2009-12-01), Hosono
patent: 2004/0105308 (2004-06-01), Matsunaga et al.
patent: 2008/0137409 (2008-06-01), Nakamura et al.
patent: 2008/0137422 (2008-06-01), Hosono
patent: 2004127346 (2004-04-01), None
Jae-Duk Lee, et al., “A New Programming Disturbance Phenomenon in Nand Flash Memory by Source/Drain Hot-Electrons Generated by GIDL Current”, IEEE, Feb. 14, 2006, pp. 31-33.

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