Method and apparatus for adaptive memory cell overerase...

Details Method and apparatus for adaptive memory cell overerase... Method and apparatus for adaptive memory cell overerase...

2011-04-19

2011-04-19

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185200

Reexamination Certificate

active

07929353

ABSTRACT:
A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more reference cells (406, 408) are connected to the word lines (402), where the one or more reference cells (406, 408) include an erased reference cell (408) connected to each word line (402). The method (500, 600) for adaptive memory cell overerase compensation includes determining an erase verify gate voltage (506, 608) utilizing the erased reference cell(s) (408) and verifying an erase voltage (514) of the memory cells (200) in response to the erase verify gate voltage (512, 614).

REFERENCES:
patent: 6735114 (2004-05-01), Hamilton et al.
patent: 2004/0257873 (2004-12-01), Shieh et al.
patent: 2006/0158940 (2006-07-01), Shappir et al.

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