Methods and structures for reading out non-volatile memory...

Details Methods and structures for reading out non-volatile memory... Methods and structures for reading out non-volatile memory...

2011-07-19

2011-07-19

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110

Reexamination Certificate

active

07983087

ABSTRACT:
A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.

REFERENCES:
patent: 5732018 (1998-03-01), Choi et al.
patent: 7489546 (2009-02-01), Roohparvar
patent: 7499329 (2009-03-01), Nazarian
patent: 2009/0109754 (2009-04-01), Schumann et al.

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