1978-10-20
1980-10-28
James, Andrew J.
357 49, 357 51, 357 59, 357 55, 357 23, H01L 2704, H01L 2712, H01L 2702
Patent
active
042310563
ABSTRACT:
A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter.
First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions. Second level interconnects include a pair of parallel interconnects connected to a respective emitter contact and orthogonal to the first interconnect.
A method of fabrication is also described.
REFERENCES:
patent: 3456335 (1969-07-01), Henning et al.
patent: 3911562 (1975-10-01), Voumans
patent: 3956033 (1976-05-01), Roberson
patent: 3998673 (1976-12-01), Chow
patent: 4037306 (1977-07-01), Gutteridge
patent: 4048649 (1977-09-01), Bohn
patent: 4085499 (1978-04-01), Kuninobu
patent: 4110776 (1978-08-01), Rao et al.
patent: 4149177 (1979-04-01), Alter
patent: 4157269 (1979-06-01), Ning et al.
Harris Corporation
James Andrew J.
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