FIR filter process and FIR filter arrangement

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S319000

Reexamination Certificate

active

07984092

ABSTRACT:
The present invention relates to a FIR filter process (1′) and to a respective FIR filter arrangement (1) wherein at least one multiplex mode is given which is characterized in that in the respective summation stage (30′) or summation block (30) partial summations are carried out and controlled in conformity with a multiplexed structure underlying a multiplexed input signal (MS) in order to obtain partial sums (Σpk-1) as accordingly filtered single signals.

REFERENCES:
patent: 4777612 (1988-10-01), Tomimitsu
patent: 4821223 (1989-04-01), David
patent: 5831879 (1998-11-01), Yom et al.
patent: 6510445 (2003-01-01), Takano
patent: 2002/0002572 (2002-01-01), Kanasugi et al.
patent: 1 039 635 (2000-09-01), None

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