Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-06-21
2011-06-21
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S118000, C716S119000, C716S132000
Reexamination Certificate
active
07966594
ABSTRACT:
The invention relates to an automated method for inserting dummy surfaces (95) into the various layers of the physical design (121) of multilayer integrated circuits organized in interconnected units (2) containing interconnected blocks (30) composed of interconnected cells (3), implemented by an integrated circuit design system (100). The multilayer integrated circuit design (121), stored in the design system (100) is implemented layer by layer, through selective insertion of patterns of dummy surfaces (95), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design (121) of the integrated circuits, by means of individual implementation of the interconnected blocks (30) and first interconnection routing (31) for said interconnected blocks (30) and individual implementation of the interconnected units (2) and second interconnection routing (22) for said interconnected units (2). The patterns of dummy surfaces are established selectively in accordance with the design of the blocks (30) of the integrated circuit.
REFERENCES:
patent: 2003/0229868 (2003-12-01), White et al.
patent: 2005/0076316 (2005-04-01), Pierrat et al.
patent: 2006/0168551 (2006-07-01), Mukuno
Blanchard Vivian
Zorrilla Marta
Bull S.A.
Dinh Paul
Miles & Stockbridge P.C.
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