Recoverable error detection for concurrent computing programs

Electrical computers and digital processing systems: multicomput – Multicomputer synchronizing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C709S201000, C709S203000, C709S208000, C709S224000, C714S012000, C714S048000, C714S100000

Reexamination Certificate

active

07925791

ABSTRACT:
The present invention provides a system and method for detecting communication error among multiple nodes in a concurrent computing environment. A barrier synchronization point or regions are used to check for communication mismatch. The barrier synchronization can be placed anywhere in a concurrent computing program. If a communication error occurred before the barrier synchronization point, it would at least be detected when a node enters the barrier synchronization point. Once a node has reached the barrier synchronization point, it is not allowed to communicate with another node regarding data that is needed to execute the concurrent computing program, even if the other node has not reached the barrier synchronization point. Regions can also be used to detect a communication mismatch instead of barrier synchronization points. A concurrent program on each node is separated into one or more regions. Two nodes can only communicate with each other when their regions are compatible. If their regions are not compatible, then there is a communication mismatch.

REFERENCES:
patent: 4816989 (1989-03-01), Finn et al.
patent: 4914657 (1990-04-01), Walter et al.
patent: 5768538 (1998-06-01), Badovinatz et al.
patent: 5987477 (1999-11-01), Schmuck et al.
patent: 6029205 (2000-02-01), Alferness et al.
patent: 6216174 (2001-04-01), Scott et al.
patent: 6430600 (2002-08-01), Yokote
patent: 6651242 (2003-11-01), Hebbagodi et al.
patent: 6718484 (2004-04-01), Kodera
patent: 7117248 (2006-10-01), Jordan, Jr.
patent: 7191294 (2007-03-01), Nakamura et al.
patent: 2005/0278620 (2005-12-01), Baldwin et al.
patent: 2006/0200730 (2006-09-01), Daugherty
patent: 2007/0174484 (2007-07-01), Lussier et al.
patent: 2007/0260909 (2007-11-01), Archer et al.
Johnson, T. et al., “Cyclical cascade chains: a dynamic barrier synchronization mechanism for multiprocessor systems,”Proceedings of the 15th International Parallel and Distributed Processing Symposium, pp. 2061-2068 (2001).
Klaiber, Alexander et al., “A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs,” retrieved at citeseer.ist.psu.edu/cache/papers/cs/7993.zSzzSzstudents.cs.byu.eduzSz˜clementzSzcs584zSzklaiber.pdf/klaiber94comparison.pdf (1994).
Invitation to Pay Additional Fees for Application No. PCT/US2007/016170, dated Feb. 19, 2008.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Recoverable error detection for concurrent computing programs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Recoverable error detection for concurrent computing programs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Recoverable error detection for concurrent computing programs will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2699219

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.