Image processing system

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G06F 300

Patent

active

057868859

ABSTRACT:
A CPU 1 and card slots 3A to 3C are connected to one another through an interface circuit 2. The interface circuit 2 effects the selection of necessary card slots and the selective supply of read and write signals. The CPU 1, the interface circuit 2 and the card slots 3A to 3C are interconnected by the data and address buses for signal transmission and reception.

REFERENCES:
patent: 3906163 (1975-09-01), Brenski
patent: 4028682 (1977-06-01), Weber
patent: 4991085 (1991-02-01), Pleva
patent: 5109517 (1992-04-01), Houda
patent: 5317748 (1994-05-01), Shimuzu
patent: 5335352 (1994-08-01), Yanai
patent: 5446869 (1995-08-01), Padgett
patent: 5513365 (1996-04-01), Cook

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