Symmetry corrected high frequency digital divider

Details Symmetry corrected high frequency digital divider Symmetry corrected high frequency digital divider

2011-04-12

2011-04-12

Lam, Tuan (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

07924966

ABSTRACT:
A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio.

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