Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-07-19
2011-07-19
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S104000, C716S105000, C716S107000, C716S111000, C716S112000, C702S127000, C702S128000, C702S129000, C702S179000, C702S180000, C702S181000, C714S703000, C714S704000, C714S705000
Reexamination Certificate
active
07984399
ABSTRACT:
In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.
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Fales Jonathan
Gumaste Udayan
Koshy Mathew
Ruehl Roland
Cadence Design Systems Inc.
Doan Nghia M
Vista IP Law Group LLP
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