Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – active junction...
Reexamination Certificate
2011-03-22
2011-03-22
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Non-single crystal, or recrystallized, active junction...
Reexamination Certificate
active
07910922
ABSTRACT:
In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
REFERENCES:
patent: 4243937 (1981-01-01), Multani et al.
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5252844 (1993-10-01), Takagi
patent: 5303199 (1994-04-01), Ishihara et al.
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5554940 (1996-09-01), Hubacher
patent: 5719449 (1998-02-01), Strauss
patent: 5742555 (1998-04-01), Marr et al.
patent: 6008543 (1999-12-01), Iwabuchi
patent: 6030890 (2000-02-01), Iwabuchi
patent: 6141245 (2000-10-01), Bertin et al.
patent: 6429029 (2002-08-01), Eldridge et al.
patent: 6429532 (2002-08-01), Han et al.
patent: 6445001 (2002-09-01), Yoshida
patent: 6534853 (2003-03-01), Liu et al.
patent: 0 564 865 (1993-10-01), None
patent: 0 767 492 (1997-04-01), None
patent: 0 813 238 (1997-12-01), None
patent: 58-015251 (1983-01-01), None
patent: 58-200526 (1983-11-01), None
patent: 02-211648 (1990-08-01), None
patent: 4-26537 (1992-03-01), None
patent: 4-96343 (1992-03-01), None
patent: 5-218042 (1993-08-01), None
patent: 07-135243 (1995-05-01), None
patent: 8-29451 (1996-02-01), None
patent: 8-64633 (1996-03-01), None
patent: 8-250498 (1996-09-01), None
patent: 8-340029 (1996-12-01), None
patent: 09-237800 (1997-09-01), None
patent: 10-092865 (1998-04-01), None
IEEE/CPMT Intl Electronics Manufacturing Technology Symposium, “Impact of Wafer Prove Damage on Flip Chip Yields and Reliability”, M. Varnau et al., pp. 293-297.
Kitsukawa Gorou
Miyamoto Toshio
Nishimura Asao
Syukuri Syouji
Coleman W. David
Mattingly & Malur, P.C.
Renesas Electronics Corporation
LandOfFree
Semiconductor integrated circuit device and manufacture thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and manufacture thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and manufacture thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2683207