Circuit and method employing an adder for sign extending operand

Details Circuit and method employing an adder for sign extending operand Circuit and method employing an adder for sign extending operand

1998-04-08

2000-05-16

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708204, G06F 750

Patent

active

060650346

ABSTRACT:
A circuit and method is provided which employs an adder for a sign extending a m bit operand. The circuit m method employs a n adder having first and second sets of n inputs and a set of n outputs. The m.sup.th bit or sign bit of the m bit operand to be extended, is inverted to generate a sign inverted m bit operand. This sign inverted m bit operand is inputted into m least significant first inputs of the n bit adder. Thereafter, a (n-m) bit operand is inputted into the (n-m) most significant first inputs of the n bit adder wherein each bit of the (n-m) bit operand represents logical 1. Additionally, n bit operand is inputted into the second n inputs of the n bit adder. The (m+1) most significant bit of the n bit operand represents a logical 1, while the remaining bits of the n bit operand represent logical 0. Upon parallel input of the sign inverted m bit operand, the (n-m) bit operand and the n bit operand into the n bit adder, the n bit adder generates an n bit output operand. The m least significant bits of the n bit operand logically equate to the m bit operand and each of the (n-m) most significant bits of the output operand logically equate to the m.sup.th most significant bit of the m bit operand.

REFERENCES:
patent: 5497341 (1996-03-01), Cohen
patent: 5691931 (1997-11-01), Nitta

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