Semiconductor device and manufacturing method thereof

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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Details

C257S613000, C257SE23033, C257SE23021, C257SE23068

Reexamination Certificate

active

07919353

ABSTRACT:
This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer12to isolate each of bump electrode forming regions11. The isolation layer12is a resist layer, for example, and is formed by exposure and development processes, for example. Each of the bump electrode forming regions11is surrounded by the isolation layer12and a protection layer10that covers a side surface of a semiconductor substrate2. Then, a printing mask16that has openings15at locations corresponding to the bump electrode forming regions11is placed above the semiconductor substrate2. Next, solder17in paste form is applied to the printing mask16. Then the solder17is applied to a metal layer9by moving a squeeze18at a constant speed. Bump electrodes19are obtained by heating, melting and re-crystallizing the solder17after removing the printing mask16.

REFERENCES:
patent: 6646289 (2003-11-01), Badehi
patent: 7633133 (2009-12-01), Noma et al.
patent: 2004/0094841 (2004-05-01), Matsuzaki et al.
patent: 2004/0113185 (2004-06-01), Shibayama et al.
patent: 2004/0209451 (2004-10-01), Kukimoto et al.
patent: 2007/0210437 (2007-09-01), Noma et al.
patent: 2009/0008798 (2009-01-01), Yoshida et al.
patent: 8-204322 (1996-08-01), None
patent: 2002-512436 (2002-04-01), None
patent: 2004-314601 (2004-11-01), None
patent: 2004-319676 (2004-11-01), None
patent: 2006-173198 (2006-06-01), None
patent: WO-2008/032566 (2008-03-01), None
International search report mailed Nov. 27, 2007, directed to counterpart international application PCT/JP2007/066707; (1 page).

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