Method of verifying semiconductor integrated circuit and...

Details Method of verifying semiconductor integrated circuit and... Method of verifying semiconductor integrated circuit and...

2011-07-12

2011-07-12

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S111000, C716S114000, C716S118000, C716S119000

Reexamination Certificate

active

07979821

ABSTRACT:
A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region.

REFERENCES:
patent: 2005/0229132 (2005-10-01), Butt et al.
patent: 2006-155524 (2006-06-01), None

Affiliated with

Also associated with

Rating

Method of verifying semiconductor integrated circuit and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of verifying semiconductor integrated circuit and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of verifying semiconductor integrated circuit and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2677213