Multi-stage successive approximation register...

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C341S118000, C341S120000, C341S155000, C341S162000, C341S172000

Reexamination Certificate

active

07999719

ABSTRACT:
A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.

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Simon M. Louwsma et al., “A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, Apr. 2008, pp. 778-786, vol. 43, No. 4.

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