Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2011-08-23

2011-08-23

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189020, C365S189050, C365S189070, C365S220000, C365S233100

Reexamination Certificate

active

08004929

ABSTRACT:
A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal command by the command latch circuit, and selects the mode latch circuit in response to the latch of an adjustment command. With this arrangement, the mode signal can be dynamically received without performing a mode register set. Therefore, when a sufficiently large latch margin of the mode latch circuit is secured, there is no risk that it becomes impossible to input the mode signal.

REFERENCES:
patent: 6185149 (2001-02-01), Fujioka et al.
patent: 6671787 (2003-12-01), Kanda et al.
patent: 2002/0003748 (2002-01-01), Fujita et al.
patent: 2002/0018394 (2002-02-01), Takahashi
patent: 2000-182399 (2000-06-01), None

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