Static information storage and retrieval – Floating gate – Particular biasing
Patent
1991-02-22
1993-11-16
Bowler, Alyssa H.
Static information storage and retrieval
Floating gate
Particular biasing
365218, G11C 700, G11C 1600, G11C 1606
Patent
active
052629856
ABSTRACT:
A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array composed of a collection of blocks, each block containing memory cells sharing the source or drain, a first region having the memory cell array formed in its surface region, and a control circuit that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential and the first region at a second potential higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential equal to or higher than the second potential and lower than the first potential.
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patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5138576 (1992-08-01), Madurawe
"A Single Transistor EEPROM Cell And Its Implementation In A 512K CMOS EEPROM." Satyen Mukherjee et al., Technical Digest of 1985 IEDM, pp. 616-619.
"A 128K Flash EEPROM Using Double Polysilicon Technology." Georghe Samachisa et al., Technical Digest of 1987 ISSCC, pp. 76-77.
"A New Hand Cell For Ultra High Density 5V-Only EEPROMs." R. Shirota et al., Technical Digest of 1988 VLSI Symposium, pp. 33-34.
"A New Flash-Erase EEPROM Cell With A Sidewall Select-Gate On Its Source Side." K. Naruke et al., Technical Digest of 1989 IEDM, pp. 603-606.
Bowler Alyssa H.
Kabushiki Kaisha Toshiba
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