Asymmetric source and drain field effect structure

Details Asymmetric source and drain field effect structure Asymmetric source and drain field effect structure

2011-07-12

2011-07-12

Bryant, Kiesha R (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

With current flow along specified crystal axis

C257SE29004

Reexamination Certificate

active

07977712

ABSTRACT:
A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.

REFERENCES:
patent: 6566204 (2003-05-01), Wang et al.
patent: 6605845 (2003-08-01), Liang
patent: 6670694 (2003-12-01), Momose
patent: 2006/0226495 (2006-10-01), Kwon

Affiliated with

Also associated with

Rating

Asymmetric source and drain field effect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asymmetric source and drain field effect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asymmetric source and drain field effect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2669840