Semiconductor integrated circuit device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S203000, C365S189150

Reexamination Certificate

active

08004904

ABSTRACT:
A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a data line, and a power-on reset circuit (64) which starts an operation in response to power-on to reset a control circuit of the nonvolatile memory. The device further has a power-on precharge circuit (66) which starts an operation in response to the power-on to perform the precharge operation of the data line. The power-on reset circuit (64) includes a first CR operation circuit (642) which produces a reset release signal indicative of change of a voltage level at a time point when a first predetermined time period (T1) elapses from the power-on. The power-on precharge circuit (66) includes a second CR operation circuit (662) which produces a precharge completion signal indicative of change of a voltage level at a time point when a second predetermined time period (T2) elapses from the power-on. The first predetermined time period (T1) is longer than the second predetermined time period (T2).

REFERENCES:
patent: 6842384 (2005-01-01), Lee
patent: 6882570 (2005-04-01), Byeon et al.
patent: 7123514 (2006-10-01), Watanabe
patent: 2003/0117847 (2003-06-01), Makuta et al.
patent: 8-314886 (1996-11-01), None
patent: 2003-242795 (2003-08-01), None
patent: 2004-5946 (2004-01-01), None

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