Plural-bit recoding multiplier

Details Plural-bit recoding multiplier Plural-bit recoding multiplier

1992-11-09

1993-11-16

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

052629767

ABSTRACT:
A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats The principles are also applied to multiplier/accumulators and complex multipliers.

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