Serial input multiplier apparatus

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G06F 752

Patent

active

052629759

ABSTRACT:
A serial-input-output multiplying circuit includes AND gates for providing partial products of an input number and a coefficient, a plurality of full adders supplied at input portions thereof with the partial products, unit delay elements for supplying carry outputs of the plurality of full adders to the input portions of the same full adders, and variable delay circuits for supplying sum outputs of the full adders to the input portions of following adders, wherein the product of the input number and the coefficient is serially obtained as a sum output of the full adder for the least significant digit.

REFERENCES:
patent: 4799182 (1989-01-01), Marwood
patent: 4839847 (1989-01-01), Laprade
patent: 4939687 (1990-07-01), Hartley et al.
patent: 5031137 (1991-07-01), Elrod

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