Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2011-07-05
2011-07-05
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230080, C365S233160
Reexamination Certificate
active
07974145
ABSTRACT:
A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.
REFERENCES:
patent: 6185151 (2001-02-01), Cho
patent: 6314536 (2001-11-01), Kurosaki
patent: 2001/0035537 (2001-11-01), Shinozaki
patent: 2005/0024956 (2005-02-01), Tran et al.
patent: 10-2007-0090447 (2007-09-01), None
Blakely & Sokoloff, Taylor & Zafman
Ho Hoai V
Hynix / Semiconductor Inc.
Tran Anthan T.
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