Field effect transistor device including an array of channel...

Details Field effect transistor device including an array of channel... Field effect transistor device including an array of channel...

2011-07-12

2011-07-12

Huynh, Andy (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S945000, C438S947000, C438S948000, C438S949000, C438S736000, C430S323000

Reexamination Certificate

active

07977247

ABSTRACT:
The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel.

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Yang-Kyu Choi, et al., “A Spacer Patterning Technology for Nanoscale CMOS”, IEEE Transactions on Electron Devices, vol. 49, No. 3, pp. 436-441, Mar. 2002.
Hari Ananthan, “FinFET—Current Research Issues”, hanantha@ecn.purdue.edu.
J. Kedzierski, et al., “High-performance symmetric-gate and CMOS-compatible V1asymmetric-gate FinFET devices”, 2001 IEEE, pp. IEDM 01-437-440.
D. Hisamoto, et al. FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Transactions on Electron Devices, vol. 47, No. 12, pp. 2320-2325, Dec. 2000.

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